Verification tools such as simulators play a vital role in efficient integrated circuit design. A circuit designer may use a simulator to verify that a design actually performs a desired function before fabricating a physical representation of that design. With the increasing complexity and expense of designing integrated circuits comes an increasing need for design verification tools which accelerate and simplify the design process.
The event-driven simulator is such a tool. In an event-driven simulator, small procedures, or functions, model the behavior of circuit elements, or cells, such as simple logic gates or more sophisticated elements such as arithmetic logic units. These procedures set the values of variables to represent nodes, such as wires or connections, within the circuit. Each node carries a signal, a unit of information in the simulation. Simulation is accomplished by setting the values of signals on nodes at the appropriate times.
In an event-driven simulator, an event is scheduled for a future time in the simulation when the simulator determines that the value of a signal on a node is to change. The information comprising an event includes the node to be changed, the new value of the signal at the node and the time at which the change is to take place. Pending events for any particular time are sorted in a prioritized event queue. The event queue provides the key list of tasks for a simulation.
In a known method of event-driven simulation, a next event is taken from the event queue. The value of the node affected is then set and every function that takes the node as an input is then evaluated. The function evaluations generate more events which are then added to the event queue.
For example, an input to an AND gate changes at simulated time T=12 nanoseconds (ns). The AND gate is re-evaluated and its output should change 2 ns later, at T=14 ns. The simulator schedules an event for the node of the AND gate output, storing its new value and time T=14 ns. The output of the AND gate is not changed immediately, since other activity may occur at T=13 ns which will use the current (not yet changed) value of the AND gate output node.
The simulator takes events in sequence, perhaps evaluating more events at T=12 ns and T=13 ns until it reaches T=14 ns. It removes the event from its list of pending changes, makes the change to the AND gate output and evaluates all the destinations of that node (the node's fanout), possibly creating more events at future times. The event information is then discarded.
With events generated in this manner, each cycle of the simulator invokes only those functions that must be evaluated. Since very few of the functions are invoked for each event, the event-driven method has the advantage of avoiding scanning a list of functions by keeping with each node a list of the functions it drives. All functions common to simultaneous events are preferably evaluated simultaneously to avoid re-evaluating the same function when only one evaluation is needed. Since modern circuits can include over a million cells, this feature of event-driven simulators is especially significant due to the long processing time required to evaluate all cell functions. It is desirable to further limit the amount of function evaluation needed during the simulation process while generating accurate results.
To allow a user to control a simulation, event-driven simulators supply a user interface. In the user interface, the user is allowed to examine nodes, set node values and re-start simulation.
If desired, a simulation can be scheduled to run for a specific amount of time with periodic interruption for the user interface. Similarly, the user interface can be invoked when certain node conditions are met or when a simulation is complete. A user interface may also be invoked when an unexpected system failure occurs.